Detailed Features: IO Engine

IOE Controller
	PCI 64-bit I/O bus 2KByte I/O read-ahead/write behind buffers PS/2 keyboard and mouse interface Ethernet interface 10/100 Mbit/Second media access controller Media independent interface to 10/100 TX transceiver Interface to Super I/O Chip for serial/parallel interface Dual high-speed serial interfaces 1284 enhanced parallel port Interface to Real Time Clock Chip Interface to Flash System ROM
ISA Bus Interface
	Connects serial/parallel PC peripherals Game port devices External Dallas DS1687 calendar clock Up to 2 MB of flash-ROM NIC serial PROM Five DMA channels are available for the serial/parallel interfaces Super I/O device provides: 2 high-speed 16C550C serial ports Clock prescalers on both serial ports Serial ports supports MIDI and normal baud rates up to 460.8Kb EPP/ECP-1284 high speed parallel port with downward compatible mode
Ethernet Interface
	10/100 BaseT Autosensing Half-duplex CSMA-CD & full-duplex circuit switched modes IP checksum computed for all received packets Multicast address filtering, using 64 bit hash buckets Flexible transmit and receive buffering Automatic transmit padding of short packets to min Ethernet length Programmable receive interrupt delay time Programmable receive gathering of short packets into single buffers Programmable inter-packet gap spacing Functional subset of IOC3 Ethernet interface Actual transmit/receive packets are stored in main memory
SCSI via 64 bit PCI Bus
	External 40Mb Fast/Wide Internal 40Mb Fast/Wide System drive One Option drive CDROM drive
I²C Interface
	Controls external codecs Hardware collision detection Software backoff/retry mechanism for bus arbitration
Video I/O
	Input Filtering/MIP-Mapping, Color Conversion, DMA Output DMA, Color Conversion, Filtering
Audio I/O DMA
	Synchronization with video
PCI Expansion Bus
	Need to describe where/how this is accessed? Next Gen? Support for up to five external 33.33 Mhz bus master devices Supports minimum of 3 64-bit slots and 2 on-board SCSI 32-bit or 64-bit Read-ahead buffers to enable high-performance DMA

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